Until recently, mobile wireless equipment used separate Integrated Circuits (ICs) for the Radio Frequency (RF) transceiver, the baseband (BB) processor and the Power Management Unit (PMU). In the context of the permanent perpetual quest for cost reduction, the approach taken by most IC vendors is that of a single chip, made up of either a single RF CMOS die, or multiple separate dies, which integrates into a single package all three previously listed ICs, namely, RF, BB and PMU into a single package.
FIG. 1 shows a typical general architecture of a multiple-band 2G/3G phone 100 consisting of a quad band 2.75G (EGPRS), triple band 3G (HSPA+) with 3G receive diversity, comprising one single die 190, of a RF Front End circuit 110, a 2G/3G RF transceiver 120, a baseband 130, a PMU unit 140 and possibly DDR memory 150, being either external or internal, plus some additional components which are all listed below:    Label 110: mobile phone's RF front-end.    Label 111: Antenna switch used for switching between different frequency bands.    Label 112: 3G (HSPA) duplexer allows connection of the TX and RX path to the antenna switch and further achieves RF isolation between RF tx and RF rx chains.    Label 113: 2.75 G (EGPRS) power amplifiers    Label 114: 3G (HSPA) power amplifiers    Label 115: Diversity receiver RF bandpass filters    Label 190: Single die/single-chip RF (label 120)-BB(label 130)-PMU (label 140) IC.    Label 120: Multi-standard, multi-band RF transmit/ receive (transceiver) IC.    Label 130: Digital baseband (DBB) IC
RF Front-End circuitry 110 supports quad band 2G (Band II, III, V, VIII EGPRS), triple band 3G (WCDMA I, II, III) which is typical of recent mobile phone architecture, the selection of the particular mode/band being performed by means of an antenna switch 111 which directs the signal to the appropriate set of front end filters 112. Conversely, antenna switch 111 directs the transmit signal generated by the appropriate 2G or 3G Power amplifiers, respectively 113 and 114, to the antenna.
2/3G transceiver 120 includes the conventional circuits required for achieving a 2G or 3G mobile communication, such as, in the receiving chain, Low Noise amplifiers (LNA) 121, a Rx VCO Frequency synthesizer 122 with appropriate division circuits (represented by local divider LO Div), a circuit 123 achieving programmable Gain amplifier (PGA), Analog to digital converter (ADC) as well as DSP processing. On the transmitting chain, transceiver 120 includes a circuit 126 achieving PGA, Digital to Analog (DAC) conversion as well as DSP processing, a Tx VCO frequency synthesizer 125 associated with dividing circuits (LO Div), and conventional digitally controlled Gain amplifier 124. Transceiver 120 further includes appropriate timing circuits 126 as well as a RF-BB baseband interface 127 for interfacing the baseband 130. For the sake of clarity, the different control, data and clock signals which are represented in FIG. 1 (such as RFBBi_EN, RX data 1, RX data 2, TX data 1, SYSCLKEN, SYSCLK) are conventional and known to the skilled man and do not need any further discussion.
Similarly, baseband 130 achieves communication between the transceiver 120 (through interface 127) with different devices and peripherals, such as two cameras 160, two displays 170, a USB device 180 through appropriate data and control leads (including CLK clocks and Chip Select CSi) as well as external DDR memory.
The integration of those components in a single die clearly reduces the cost of manufacturing a handset since the telecom pipe of the mobile phone now only requires very few extra additional components to make a phone call: one or several Power Amplifier(s) (PA) and its associated front-end circuitry such as RF bandpass filters, duplexers, antenna switch etc.
However, despite the significant cost saving resulting from the use of a single RF-BB-PMU chip, some significant EMI problems need to be considered in order to prevent the RF receiver as well as the RF transmitter chain from being polluted by digital BB and external memory bus noise, as well as associated clock spurs, and their multiple harmonics.
The present application particularly relates to the protection of the 2G receiver chain, identified in FIG. 1 as being the victim. In FIG. 1, the victim suffers from multiple sources of aggression which can be sorted into two categories:                Wideband noise source aggressors: falls into this category, noise generated by high speed data transfers between the single chip and its peripherals, such as camera, displays but also, USB and external memory interface (blocks 150, 160, 170, 180)        Narrowband spurs: falls into this category, either clock harmonics spurs, or pulsed clock source and their harmonics.        
Some solutions are known in the art for reducing the effects of such additional spurs.
A first known solution consists in protecting the victim by carefully designing the LNA and systematically using differential wires in order to make best benefit of the common mode rejection of such a differential architectures.
A second known solution is based on the use of sophisticated packages (eg. so-called flip chip package) for embodying the RF transceiver integrated circuit may reduce the coupling between the input wire of the LNA and the digital interface, which coupling generally increases with the frequency.
All those techniques clearly tend to increase the design and manufacturing costs of the transceiver IC.
In some situations, those techniques do not allow to avoid desensitization of the receiver in some circumstances. In particular, it has been shown that multiple integer harmonics of the reference clock used to transfer data over the external memory interface desensitize an RF receiver.